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AMD patent suggests it is looking closely at hybrid CPU designs

by Mark Tyson on 10 August 2020, 11:11

Tags: AMD (NYSE:AMD)

Quick Link: HEXUS.net/qaenjt

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An AMD patent application document has come to light which could provide some interesting indications of one way new CPUs may be designed by the firm in the coming months / years. The US patent document concerns an "Instruction subset implementation for low power operation". Computing and prog rock music fan Underfox of Twitter unearthed this document at the weekend and shared a link to the patent PDF.

In brief it seems that AMD is trying to patent a heterogeneous processor which mixes full or "high-feature" CPU cores with "low-feature" CPU cores implementing a subset of ISA features. The obvious reference to Arm's 'big.LITTLE' implementation is made by Underfox, and you can cast an eye at Intel's Lakefield hybrid architecture too, if you are looking for inter-industry comparisons.

Another detail that makes AMD's patent look similar to ideas already in use by Arm and Intel is simply the purpose of the hybrid architecture - power saving. "The lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance that the first processor," sums up the abstract.

AMD's background detail in the patent discusses the appeal of this hybrid architecture in mobile computing - with its wide performance range targets according to workload requirements. In mobile computing battery life is a major consideration.

In the proposed architecture, low-feature processor cores will be able to turn off high-feature processors when not in use. It is thus important that the low-feature cores have support for various low-priority processes that run frequently if not constantly - OS maintenance, timer support, monitoring functionality and so on.

Various figures are provided in the patent document. One shows how the low-and high-feature processor clusters have a shared cache, controller and main memory access. For communication between the core clusters there are several options available and illustrated in patent diagrams.

Last but not least please remember that patent applications don't necessarily result in finished shipping products.



HEXUS Forums :: 7 Comments

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Would a patent even be able to be granted since ARM's big.LITTLE already exists as a prior example?
People call big.LITTLE as a generalised term and I see no reason why this patent wouldn't be permitted because it is around the handling of high and low featured cores and their interaction across the greater package.

As I understand it, ARMs big.LITTLE architecture is consistent between the small and big cores and anything extra is extraneously accessed and the small cores are just literally “small” cores but are the same as the big ones?
Output
Would a patent even be able to be granted since ARM's big.LITTLE already exists as a prior example?

This isn't big.LITTLE

I'm guessing the “small” cores here would have ripped out all the 16/32 bit support and all the garbage x86 CISC baggage like repeat instructions and complex addressing modes that even Intel have told us to avoid for decades.

It if tries to run an old/complex instruction, the CPU saves context with an illegal instruction trap and the thread gets restored onto a full x86 CPU. That would need OS support, but Linux could adopt that quite quickly so could be interesting for cramming more cores into a server power envelope.
With the way that MS is making windows arm and x86/x64 compatible I've always wondered why AMD haven't pushed harder with making a combo chip (they supposedly were at one point according to google) with both types of cpu's or even an amd cpu with ‘x86’ instructions co-processor, to offset the impact of virtualisation.
DanceswithUnix
This isn't big.LITTLE
I was assuming it would count as similar enough to be considered as having prior examples.

I guess it just depends upon how detailed the patent application is. Probably because most times I hear about patents, it's usually the vague “how did that ever get granted?” type attempting to be used by patent trolls.

DanceswithUnix
I'm guessing the “small” cores here would have ripped out all the 16/32 bit support and all the garbage x86 CISC baggage like repeat instructions and complex addressing modes that even Intel have told us to avoid for decades.

It if tries to run an old/complex instruction, the CPU saves context with an illegal instruction trap and the thread gets restored onto a full x86 CPU. That would need OS support, but Linux could adopt that quite quickly so could be interesting for cramming more cores into a server power envelope.

It will certainly be interesting to see how things play out. Obviously Intel has something upcoming, and this indicates that AMD does too - even if the article does state that it doesn't guarantee that AMD will make something based on the patent, I suspect it's likely to happen at some point so both companies have another thing to compete against each other with.