Lesson time
CMOS
Time for the technical bit, then. We'll start with a quick lesson on MOS transistors. Metal Oxide Semiconductor transistors are a key component in just about any electronic circuit. They are the 'switches' of micro electronics, providing the basis for the binary logic we use in computers. Here's a cross section of a MOS transistor, courtesy of Intel's Penryn press presentation.
Silicon is the main component of a MOS, of which you'll see two 'types'. We have a p-type region of silicon, and an n-type region. A p-type region has a surplus of positive carriers within its lattice, while an n-type region has a surplus of electrons. Put these two together and depending on how you apply fields and currents, you can do the funky stuff that lets us make computers.
In the above image the area marked 'silicon substrate' will be either n-type or p-type. The areas marked S (source) and D (drain) will be the opposite of the substrate. An n-type MOS has n-type source/drain regions, whilst the p-type MOS has p-type source/drain regions. Create a circuit between source and drain with a positive voltage at the source, and nothing much will happen... there's a region between them preventing current flow.
Now cast your eyes to the bit atop the silicon. The first, thin layer is a Silicon Oxide layer; it's an insulator. Next we have a polysilicon gate, comprising the same type of silicon as the source/drain regions. Above that we have a layer of something with a low resistance. These three parts form the 'gate' of the transistor. If a voltage is applied here, an electromagnetic field creates a 'channel' within the silicon substrate that allows electrons to flow from source to drain (and so allows current to flow the other way, as we perceive it). Increase the voltage at the gate and more current can flow; if the gate voltage isn't high enough, then the field will be weakened and the channel will be saturated, causing current to be restricted.
So, now you should be able to see how a transistor can form a switch for a circuit. Create a voltage at the gate and you can turn the switch 'on'. Because of the insulating layer, no current flows from the gate into the transistor, which is great news. Of course, in real life it's not that easy.
On their own, a p-type or n-type MOS don't provide particularly good switching for binary logic. However, both types can be combined to produce very good binary signalling. The two types complement each other, and so we have the Complementary MOS, or CMOS. With several CMOSes, we can build logic gates and from there create clever electronic circuits. But the best bit about CMOS, is it only takes power to switch the state of a CMOS unit, so if it's sat idle, it shouldn't use any power.
Alas, even when a MOS is 'off', there can be some current leakage from drain to source, and there's even leakage through the gate too. Oh dear. It's one of the many problems manufacturers face when trying to increase processor speeds without creating loads of heat and consuming masses of power.
Enter high-k and metal gate
So here's how Intel's reducing some of these CMOS menaces in Penryn.
The yellow area in this MOS is a high-k dielectric, that can be thicker than good old SiO2 without compromising the field created at the gate. The polysilicon gate is gone and in its place is metal. This metal gate increases the field effect of the gate. Intel says they've found a great combination of high-k dielectric and metal gate materials that gives them good field strength and insulation, thus reducing both source-drain and gate leakage, which means they can rock on with faster chips that are energy efficient. They're keeping under their hats the materials they're using, however... can't blame them for that!
Penryn
Intel had an SRAM chip using 45nm high-k and metal gate technology in early 2006. Now they've got full-on 45nm CPUs out of the fab and working. Here's some silicon porn for you:
Dual-core Core2 processors based on Penryn will have a meaty 410 million transistors on board, while quad-core versions will have 820 million (duh). There'll be larger caches, SSE4 instructions and of course, quicker chips. Performance per watt should improve once more.
In another two years Intel should be down to a 32nm process, keeping up with good ol' Moore's Law. For now, you're hopefully a little wiser about some of the terms you'll hear Intel and indeed other CPU manufacturers using from here on in.
