As a precursor to our upcoming MSI K7D Master review we thought it would be a good idea to take a look at the underlying technology that makes the board possible, in particular the chipset. AMD are a relative newcomer to the multi-processor arena with AMD CPU's traditionally used in uni-processor systems and it's only recently with the launch of the AMD 760MP and the chipset we are covering today, the 760MPX that AMD have offered a multi processor chipset for use with their CPU's.
Chipset support for multi processor systems is one thing but the CPU also needs to have certain features present before it can be used with a supporting chipset. To take one of these features as an example where the x86 architecture is concerned, there are a number of interrupt request lines (IRQ's) present in the system managed by the CPU. Hardware attached to the host bus that the CPU is connected to can raise interrupts on these IRQ lines and the CPU responds to the request. Simplified, this is how modern x86 systems work. The hardware, a graphics card for example, raises an interrupt on an IRQ line to signal to the CPU that it is ready to use the bus and send or recieve data (or both!) on the bus and the interrupt tells the CPU to manage that request.
This is fine with a single CPU when one CPU manages the single set of IRQ lines in the system and there isn't any complication (well, none that concerns us!). However when you add more processors to the system things get interesting. In the case of 2 CPU systems like we are looking at here, 2 CPU's have to manage one set of IRQ lines and therefore coordinate their operation. For example, say we have a graphics card sitting on IRQ15 and it raises an interrupt, what CPU should handle the request?
Special logic on the CPU called the IO APIC is mainly responsible for managing all the extra complication that arises from running more than one processor. When the machine boots, the BIOS is responsible for initialising the APIC logic on the CPU amongst other things. The operating system upon loading must also be able to work properly with 2 CPU's including managing the IRQ lines in software since the drivers in the operating system tell the hardware to raise an interrupt.
It's these added complications that give rise to processing overheads and are the reason why running more than one processor doesn't simply double performance. For each extra CPU added to an x86 system there needs to be extra management overhead for that CPU. This is the reason why some multi processor systems don't scale very well since the underlying architecture for the processors experiences the law of dimishing returns where the performance gained from adding a CPU is wiped out by the management overhead for it.
So we know that adding a processor to a system can be beneficial but there are trade-offs. It's the job of the managing chipset, in this case the 760MPX, to keep these overheads to a minimum and make sure that running a second CPU is worth the cost and effort. The actual mechanics of a multi processor system have been greatly simplified here and we could devote entire articles just to the intricacies of multi processor operation.
So let's take a look at the chipset and see if it does things right. It is AMD's flagship multi processor chipset so they can't afford to get it wrong.
The AMD 760MPX Chipset
Before we dive head first into the MPX version of the chipset, it's worth noting that there's a previous version of the chipset called the 760MP. The difference is in the southbridge and when there's a difference to highlight when we cross that bridge (pun intended? you decide!) we'll discuss it a bit further.
First off, lets take a look at a diagram of the chipset before we talk about things further.
Being a usual chipset design we have both north and south bridges. Lets take a look at the spec of both.
AMD 762 System Controller
So we can see that the 760MPX features the 762 northbridge and 768 southbridge. This differs from the 760MP which used the 766 southbridge. So we can see that both versions of the chipset used the same northbridge which means an identical memory controller, AGP interface and the two seperate point to point busses for the CPU's.
AMD 768 Peripheral Bus Controller
- Two 266 MHz point-to-point AMD system buses, providing uniprocessor or two-way symmetric multiprocessor capability
- PC2100 DDR (Double Data Rate) Memory Controller with support for up to 4 GB of memory space (supports four Registered DIMM slots)
- AGP-4X Interface (supporting 1X and 2X modes)
- Dual Mode PCI 2.2-Compliant PCI Bus Interface
- 66-MHz clock with 32-bit and 64-bit data path support (supports up to two PCI slots)
- 33-MHz clock with 32-bit and 64-bit data path support (supports up to seven PCI devices)
- A 949-pin Ceramic Column Grid Array (CCGA) package
- 2.5 V Core
- Host (primary) PCI bus utilizing a 66MHz/32-bit interface (PCI 2.2 Compliant)
- Secondary 33MHz/32-bit PCI bus interface (PCI 2.2 Compliant), including PCI bus arbiter with support for up to eight external devices
- AC ‘97 Soft Audio Controller
- UDMA 33/66/100 compatible EIDE bus master controller:
- OHCI-based USB host
- Extensive ACPI-compliant Power Management logic:
- Privacy/security logic, including ROM access control
- Thirty-two General Purpose I/O (GPIO) pins (Many pins are multiplexed with other hard-wired functions.)
- Legacy-AT Compatible Logic:
- Interrupt Controller (8259-based)
- Programmable Interval Timer (8254-based)
- DMA Controller (for LPC bus)
- Legacy Ports
- Real-Time Clock (RTC):
- I/O APIC Controller
- Support for Distributed DMA and serial IRQ protocols
- SMBus controller with one SMBus port
- Random Number Generator
- A 492-pin BGA package; 26x26 BGA grid; 35x35 millimeters square
- Both 2.5-volt core and 3.3-volt output drivers; 5-volt tolerant input buffers
The difference in the newer chipset focuses mainly on the PCI bus interfaces. The north and southbridge use the PCI bus to communicate with each other and therefore must provide a PCI bridge to implement further PCI busses on the system. With the old 762 southbridge it was a 33Mhz 32/64-bit PCI bus between the north and south bridges. With the old 766 southbridge the bus ran at 33MHz. So we have a doubling in available bandwidth provided the 2 devices you can put on the same bus run at 66Mhz. That's right, the bus is shared with 2 possible devices and if any of them don't run at the top spec supported, the whole bus drops in spec and the interconnection between the host bridges slows.
The 768 southbridge also provides a secondary 33MHz 32-bit PCI bus interface for regular devices. The improved PCI bridge interface and the addition of the extra PCI bus on the southbridge (eagle eyed chipset spotters will also have seen the AC'97 audio on the 768 too) are the main additions to an already powerful chipset.
The seperate EV6 bus per CPU is a big benefit to the overall performance of the chipset when running in multi processor configuration. Traditionally on Intel dual processor chipsets, the CPU's shared the same bus connection to the northbridge whereas on the 760MP/760MPX, each CPU gets a dedicated 266MHz point-to-point DDR bus connection to the bridge. Paired with a high performance 266MHz DDR memory interface and memory controller.
Reading from an Anandtech article on the 760MP chipset we can also glean that the chipset implements cache coherency using the northbridge. Since the processors dont share a bus connection to the bridge the CPU's use the northbridge to copy cache data between themselves when needed. This needs to happen when a request for data hits the processors. Both CPU's snoop the bus for cache data requests and can copy the data to each other as needed using the northbridge.
So with each CPU having its own dedicated path to the processor the system is able to do more work since the CPU's aren't fighting over usage of the same data path to the bridge. The overall memory bandwidth of the system hasn't increased over 2.1GB/sec which is the maximum supplied by PC2100/DDR266 memory. That's the only downside to the system. With both CPU's each being able to use that 2.1GB/sec individually under heavy load but it also leaves no bandwidth for the peripheral devices either.
You need extreme conditions to satiate the need for 2.1GB/sec but it may well occur under the condition the chipset is designed for. A twinbank DDR333/400 version of the memory controller giving 5.4GB+/sec of memory bandwidth, would suit the chipset better but in benchmarks performed on 760MPX production, the apparent lack of bandwidth doesn't seem to hurt things very much.
We've just discussed the chipset as it looks on paper with no benchmarks. We'll be taking a look at a board featuring the chipset soon so we'll leave the benchmarks for that. This article is designed as a lead up to the review.
On paper, looking at the main features including independant point-to-point buses for the CPU's, improved PCI bus bridge link and the extra features on the 768 southbridge, the 760MPX seems a worth upgrade to the 760MP. It addresses some of the major concerns high end board vendors and customers had with the initial boards based on the chipset and high end performance users are more willing to take a chance on what is essentially still a first revision on a new chipset from a manufacturer with no prior experience in this arena.
What a debut chipset it is tho. They seem to do a lot of things right and not much wrong. We'll see how a board performs in the near future and future revisions and evolutions of the chipset should take AMD further into a market they seem keen to play in. ServerWorks and Intel are tough competition so good luck!
If you want to do a bit more research under your own steam, I suggest the following as starting points.
AMD-760™ MPX Chipset Tech Docs [AMD.COM]
AMD's 760MPX Chipset - Multiprocessor for the Masses [ANANDTECH.COM]
The AMD-760™ MPX Chipset Product Overview [AMD.COM]