A new technique in transistor design promises to drastically cut the power consumption of many electronic devices, especially miniature battery-powered tech gadgets. In essence the new process, developed by a company called SuVolta, reduces the variability in voltages required by transistors on the same chip. Chips following SuVolta’s technique have much less voltage variation within their design and can operate with a lower voltage, saving power. In fact SuVolta boast chip designs which use “half the power” to provide “all the performance”.
Importantly SuVolta’s technology is compatible with existing manufacturing equipment and can be integrated into existing processes (between 65nm and 20nm) and design tools. The name of SuVolta’s key technology which is leveraged to give these lower power benefits is ‘DDC™ Technology’. DDC is an acronym for Deeply Depleted Channel. The company details DDC thoroughly here. In brief SuVolta describe DDC as follows “DDC technology enables the reduction of both leakage power and active power consumption, primarily by addressing transistor threshold voltage variation and carrier mobility issues.”
Using DDC designers can ‘Powershrink’ designs for 30 – 50 per cent lower active power and 50 – 60 per cent lower leakage power. DDC ‘DesignBoost’ allows designers to keep current designs and replace old “leaky transistors” with SuVolta designs. There is also a design option to boost chip performance rather than use the efficiency to cut power demands. Please refer to the power/performance chart below.
This new DDC technology has recently been adopted by Fujitsu to produce an image processing chip - the ‘MB86S22AA Milbeaut’. This Fujitsu chip started volume production last week. Also MIT Technology Review reports that SuVolta has “four other undisclosed partnerships with chip manufacturers”. Any technology that makes my mobile and tablet batteries endure longer is very welcome.