So why should the Venice core (aka E3-stepping) potentially be any better than the Winchester (90 nm) and Newcastle (130nm) cores for overclocking? I'll answer the question with a look at the Venice's new attributes.
Venice is based on the same 90 nm manufacturing process as the Winchester core, and it carries the same SOI (Silicon-On-Insulator) technology that it now to be found on all Athlon 64s. The SOI process attempts to hasten gate switching by locating the CPU's transistors on top of an insulating layer, which, in this case, is silicon oxide. By having a layer in between, the capacitance (time taken to charge and discharge) is greatly reduced, allowing for faster switching.
Carrying on from the above, Venice cores are also recipients of what AMD and IBM term Dual Stress Liner technology. It's very similar to Intel's strained silicon technology. However, DSL uses a novel approach by stretching silicon atoms in one type of transistor and squeezing them in another (n- and p-channel transistors, respectively). AMD and IBM claims up to a 24% increase in switching speeds when DSL is implemented, higher than Intel's strained silicon approach. Add this to the benefits of SOI, discussed above, and AMD is confident that select Venice- and San Diego-based (only differentiated by carrying 1MB L2 cache) cores can comfortably scale to 2.8GHz.
From a pure hardware point of view, revision E Athlon 64s also benefit from SSE3 instruction support. SSE3 support for Pentium 4 Prescotts adds 13 extra instructions to SSE2's set. AMD's Venice core carries 11 of these 13, omitting, for obvious reasons, MONITOR and MWAIT instructions that pertain to the Prescott's Hyper-Threading technology. The problem with SSE3 for both Intel and AMD CPUs is the lack of software that can currently take advantage of its parallel processing ability.
Improved memory controller
It seems as if every iteration of the Athlon 64's contains a slightly better memory controller. Venice core CPUs' memory controller offer greater compatibility with DIMMs. For example, it can now address four DIMMs with the performance-enhancing 1T command. Further, one can now use DIMMs of different sizes in a single memory channel, and use four double-sided DIMMs at DDR400 speeds.
Whilst SSE3 and an improved memory controller will help in certain circumstances, the keen enthusiast will be far more eager to see how DSL and SOI technologies combine to lower the Athlon 64's heat output and raise frequency headroom.
|Model Number||Athlon 64 3000+||Athlon 64 3200+||Athlon 64 3500+||Athlon 64 3800+||OPN||ADA3000DAA4BP||ADA3200DAA4BP||ADA3500DAA4BP||ADA3800DAA4BP||Clock speed||1.8GHz||2.0GHz||2.2GHz||2.4GHz||Cache||512KB||512KB||512KB||512KB||Voltage||1.35/1.4v||1.35/1.4v||1.35/1.4v||1.35/1.4v||TDP||67w||67w||67w||89w||Current price||£105||£130||£179||£249|
The Venice core CPUs range from the Athlon 64 3000+, the CPU in for review today, up to the 3800+ model. Let's take a physical look.