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Intel explains architecture that could scale to 1,000 cores

by Pete Mason on 23 November 2010, 11:19

Tags: Intel (NASDAQ:INTC)

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Even though the majority of the developments coming out of the Supercomputing Conference 2010 in New Orleans are highly theoretical, they give an interesting peek into the sorts of technology that might one day see the light of day. The latest of these pieces of futurology comes from Intel, who has demonstrated a CPU design that could scale to more than 1,000 cores.

The design is the basis for the company's Single-Chip Cloud Computer (SCC) which was revealed last year in the form of a prototype 48-core, 125W, 45nm processor. The CPU got its name because of the way that the cores are linked together via a high-speed on-chip network - much the same as nodes in a data-centre would be connected.

Since performance wasn't particularly important - this is just a research exercise, after all - the engineers used a derivative of the original Pentium processor design for each individual core. Pairs of cores were then tiled in a six-by-four array and connected by a 'mesh' on-chip network via an on-board router.

What all this means is that instead of relying on cache to communicate - and running into problems ensuring that each core has equal access to on-board memory, known as cache coherency - messages can be passed directly between processing cores. In terms of programming and design, the chip acts very much like a 48-node cluster, rather than a traditional CPU.

According to Intel's Timothy Mattson, the result is an "arbitrarily scalable" architecture "that could, in principle, scale to 1,000 cores". Only at this point would the size of the mesh begin to negatively impact performance.

Chips like the SCC are obviously still experimental, and Intel has no plans to start including them on any roadmaps at this point. However, it provides an interesting take on how the difficulties of adding more cores onto a single CPU might be tackled.

More details on the chip can be found in a paper (PDF) published by the researchers for the conference. Alternatively, IDG has posted an in-depth write-up of the technology.



HEXUS Forums :: 5 Comments

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Could potentially work well where CPU performance isn't key, but threading is perhaps. Will be interesting to see where they go with it.
Arbitrarily scalable… up to 1000 cores. So, not all that arbitrary then.
Well it sounds like it could go higher but you'd start losing performance so it would make no sense - so maybe arbitrary then ;)
1,000 is an arbitrary figure, probably plucked out of thin air for the press release.
so a 6x4 tile of 2 cores is 48 cores. Scaling this logically would we taking these tiles and making a 6x4 platter of them, giving you 24x 48-cores. Meaning 1152 cores in total.

It's never going to be a nice 1,000 cores, just like CPU speed is never actually a nice round 2GHz or whatever.
I think arbitary means you can have 43 cores, 139 cores etc, any number of cores rather than fixed multiples. yes I know they come in tiles however I expect defective cores will be disabled to increase the yield of usable processors.